As the use of electronic devices, such as personal computers, continues to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices such a notebook computer, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continue to increase, the power consumed by such devices has continued to increase in a corresponding manner. Therefore, many attempts to reduce the power consumed by an electronic device have focused on reducing the power consumption of DRAM devices.
In general, the power consumed by a DRAM device increases with both the capacity and the operating speed of the DRAM devices. The power consumed by DRAM devices is also affected by their operating mode. A DRAM device for example, will generally consume a relatively large amount of power when the memory cells of the DRAM device are being refreshed. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. A relatively large amount of power is consumed when refreshing a DRAM because rows of memory cells in a memory cell array are being actuated in the rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated. As a result, DRAM refreshes tend to be particularly power-hungry operations. Further, since refreshing memory cells must be accomplished even when the DRAM is not being used and is thus inactive, the amount of power consumed by refresh is a critical determinant of the amount of power consumed by the DRAM over an extended period. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
Refresh power can, of course, be reduced by reducing, the rate at which the memory cells in a DRAM are being refreshed. However, reducing the refresh rate increases the risk that data stored in the DRAM memory cells will be lost. More specifically, since, as mentioned above, DRAM memory cells are essentially capacitors, charge inherently leaks from the memory cell capacitors, which can change the value of a data bit stored in the memory cell over time. However, current leaks from capacitors at varying rates. Some capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit. These defective memory cells can be detected during production testing, and can then be repaired by substituting non-defective memory cells using conventional redundancy circuitry. On the other hand, current leaks from most DRAM memory cells at much slower rates that span a wide range. A DRAM refresh rate is chosen to ensure that all but a few memory cells can store data bits without data loss. This refresh rate is typically once every 64 ms. The memory cells that cannot reliably retain data bits at this refresh rate are detected during production testing and replaced by redundant memory cells.
One technique that has been used to prevent data errors during refresh as well as at other times is to generate an error correcting code “ECC,” which is known as a “syndrome,” from each item of stored data, and then store the syndrome along with the data. When the data are read from the memory device, the syndrome is also read, and it is then used to determine if any bits of the data are in error. As long as not too many data bits are in error, the syndrome may also be used to correct the read data. Some DRAM devices include a mode register that may be set to selectively operate the DRAM device in either a normal mode or an ECC mode.
The use of ECC techniques can allow DRAM devices to be refreshed at a slower refresh rate since resulting data bit errors can be corrected. The use of a slower refresh rate can provide the significant advantage of reducing the power consumed by DRAM devices. Prior to entering a reduced power refresh mode, each item of data is read. A syndrome corresponding to the read data is then generated and stored in the DRAM device. When exiting the reduced power refresh mode, the each item of data and each corresponding syndrome are read from the DRAM device. The read syndrome is then used to determine if the item of read data is in error. If the item of read data is found to be in error, the read syndrome is used to correct the read item of data, and the incorrect item of data is then overwritten with the corrected item of data.
The use of the above-described ECC techniques to allow refresh at a relatively low rate can markedly reduce the power consumed by DRAM device in many applications, particularly where the DRAM device is not being accessed for an extended period. However, if the DRAM device is being frequently accessed, the power consumed in reading syndromes and data, using the read syndromes to check and possibly correct the read data, and writing any corrected data to the DRAM device can exceed the power saved by using ECC techniques to refresh at a reduced rate. Moreover, it can require a considerable period of time to exit the reduced power refresh mode when using ECC techniques as described above, thus preventing data stored in the DRAM device from being quickly accessed. As a result, there are many applications where a reduced power refresh mode using ECC techniques are not practical.
For example, one application in which reduced power consumption is very important, but access to a DRAM device is frequent, is in the field of cellular telephones. DRAM devices are frequently used in cellular telephones to store a variety of data, such as paging protocols, text messages, image data, etc. When the cellular telephone is powered but a telephone call is not currently active, the cellular telephone is essentially inactive. During such periods of inactivity, almost all of the data stored in the DRAM device is not being accessed. However, a small portion of the data stored in the DRAM device must be accessed any time power is applied to the cellular telephone. For example, data corresponding to a paging protocol must be accessed to determine if a call is being made to the cellular telephone. The protocol data is accessed during each paging period which occurs on a periodic basis, such as once every one-half second. During the paging period, the cellular telephone uses the protocol data to transmit a probe, which is received by one or more cellular sites that are in range of the cellular telephone. A cellular site then transmits a message back to the cellular telephone if an incoming call to the cellular telephone is being made.
The need for at least some data stored in DRAM devices to be frequently and immediately available makes it impractical to use the previously described ECC techniques to reduce power in an extended refresh mode. The use of such techniques would require the DRAM device to enter and exit the reduced power refresh mode ever paging period, which, as mentioned above, is on the order of once every one-half second. As a result, the read data stored in the DRAM device might not be accessible when the data were needed, particularly if the DRAM device contains a large number of memory cells. Even if the DRAM device could enter and exit the reduced power refresh mode at a sufficient rate, the time required to enter and exit the reduced power refresh mode might very well reduce the duration of the reduced power refresh period to the extent that very little power was saved. As a result, DRAM devices used in cellular telephones generally are operated with faster refresh rates than otherwise needed as a result of the need for the entire device to become active so that the protocol data can be accessed every paging period. However, doing so causes the cellular telephones to consume substantial power, thereby reducing the useful life of batteries powering cellular telephones before a recharge is needed.
There is therefore a need for a memory system and method that is effective in allowing a DRAM device to operate in a reduced power refresh mode using ECC techniques, but does so in a manner that does not delay access to data stored in the DRAM or minimize the benefits of operating in the reduced power refresh mode.